1. Field of the Invention
The invention relates in general to a method of fabricating a dielectric layer. More particularly, this invention relates to a method of fabricating a capacitor with a high capacitance.
2. Description of the Related Art
The current trend of memory fabrication process for an integrated circuit includes increasing the storage density and the data storage amount on a single chip. A higher density provides a memory with a more compact storage. In addition, to store data into a single chip is more economic compared to store the equivalent amount of data to multiple chips. The density of integrated circuit can be increased via shrinkage of structures, for example, conductive lines or transistor gate, and reduction of spaces between structures. In the fabrication of integrated circuit, the shrinkage of circuit structure can be treated as a reduction of design rule.
The reduction of design rule results in a reduced substrate surface area, and consequently, the available area for fabricating the storage capacitor of a dynamic random access memory (DRAM) is restricted. This limits the storage capacitance of the DRAM. The limitation on storage capacitance leads various problems such as mechanical deterioration and leakage current or even potential loss caused by larger dielectric susceptibility. Furthermore, the loss of storage charges caused by larger dielectric susceptibility may result in a more frequent refresh cycles. While refreshing, the data accesses such as read and write operations can not be processed. Thus, a frequent refresh cycle requires a more complex data access scheme or a more sensitive charge sense amplifier. To increase the capacitance of a capacitor and to resolve the problems mentioned above, a three-dimensional capacitor has been developed. However, considering a high yield and a high throughput, the kind of capacitor structure is complex and difficult to fabricate.
In addition to a three-dimensional capacitor, methods including minimize the thickness of the dielectric layer and using a dielectric layer with high dielectric constant may also achieve the objective of increasing capacitance. However, the method of fabricating a thin dielectric layer is still under developed due to the consideration of uniformity and reliability. In contrast, many approaches have been made for the application of using a dielectric layer with a high dielectric constant. For example, tantalum oxide (Ta.sub.2 O.sub.5) with a dielectric constant three times larger than silicon nitride has been widely applied. One major problem in employing tantalum oxide is the very significant leakage current. To solve such problem, methods have been disclosed, for example, in U.S. Pat. Nos. 5,444,006, 5,508,221, and U.S. Pat. No. 5,786,248. In these prior art, attention has been drawn upon the leakage current induced by a mutual interaction between the tantalum oxide layer and a bottom electrode. Therefore, an oxide layer or a nitride layer is formed to block the mutual interaction, so as to mitigate the occurrence of leakage current. It is known that the dielectric layer is formed as a thin film between the bottom electrode and the top electrode. Therefore, apart from the mutual interaction to the bottom electrode, the dielectric layer also has a mutual interaction with the top electrode. Therefore, the reduction in leakage current using the conventional method is limited. For the semiconductor devices fabricated with a higher and higher precision by more and more advanced technique, this limit amount can hardly cope with the requirements.